1. Field of the Invention
The invention relates to a method of manufacturing a semiconductor device comprising a dual gate field effect transistor.
2. Description of the Related Technology
A method of manufacturing a semiconductor device comprising a dual gate field effect transistor is known from U.S. Pat. No. 6,580,137 B2 that has been issued on Jun. 17, 2003. Therein (see e.g. FIG. 12B and the description columns 7 to 14) a method is described in a dual gate transistor is provided in a trench. One of the gate regions is formed at the bottom part of the trench while the other gate region is formed in the upper part of the trench, the channel region being interposed between the two gate regions.
A drawback of the known method is that it is rather complicated and requires relatively many steps. Thus, there is still the need for a method for forming a dual gate transistor which can be easily incorporated in present and future CMOS technology.